Integrated circuit (IC) chips and other semiconductor devices are often packaged using lead frames. Lead frames include a number of metal leads (or pins) that extend outward from an enclosure in which a semiconductor die (or chip) is disposed. Deployment of the semiconductor device often involves soldering the pins to a printed circuit board.
Wire bonds are typically used to establish electrical connections between the pins and the semiconductor die. In wire bonding, bond wires are attached to bond pads located on the semiconductor die. The bond wires generally do not overlap. In this manner, short circuits may be avoided.
Lead frame packaging is complicated by disposition of multiple die in the same package. One complication involves the presence of die-to-die wires, which may increase the likelihood of wire crossings and short circuits. Other complications involve the inefficient allocation of pins. For example, the multiple die may have a number of pins in common. For example, ground and power supply pins may be duplicated across the multiple die.
The number of duplicative pins may increase substantially in multiple die packages in which the multiple die are identical or similar. Such duplication may lead to artificially high pin counts. For these and other reasons, the resulting package may be excessively or undesirably large.
Attempts to address the multiple die complications may present other issues. One approach involves mounting the multiple die on a common substrate. But such substrate packages unfortunately often introduce thermal limitations. For instance, the substrate typically impedes heat dissipation.